CACHE MEMORY CONTROL SYSTEM

PURPOSE:To shorten a write access cycle and to improve the information processing throughput of the system by writing data in both a cache memory and a storage device before a hit of a cache is decided. CONSTITUTION:In any write access, the data is written in both the main storage device 6 and cache...

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Bibliographic Details
Main Authors WATABE KEN, KONDO NOBUKAZU, AOTSU HIROAKI, YU KEIICHI
Format Patent
LanguageEnglish
Published 23.05.1991
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To shorten a write access cycle and to improve the information processing throughput of the system by writing data in both a cache memory and a storage device before a hit of a cache is decided. CONSTITUTION:In any write access, the data is written in both the main storage device 6 and cache memory 5 before the hit of the cache memory 5 is decided, and if a mishit is decided, significant bits in an address array are set to '0' and the entry is made invalid. The data is written in the cache memory 5 to shorten single write cycle length before the bit of the cache memory is decided. When the hit rate of a program is high, the shortening of one write cycle is more effective to the processing time than a decrease in hit rate by making the cache memory 5 invalid, so the performance of the whole system is improved.
Bibliography:Application Number: JP19890257661