MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• Main Authors: IGARASHI SHIGEKI, KAWANOBE TORU
• Format: Patent
• Language: English
• Published: 02.05.1991
• Subjects: BASIC ELECTRIC ELEMENTS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; SEMICONDUCTOR DEVICES

PURPOSE:To decrease the number of manufacturing processes in a TAB (a Tape Automated Bonding) by a method wherein marks are formed at prescribed places on a film in a process prior to a process of sealing a semiconductor chip with a potting resin. CONSTITUTION:The element formation surface and the side surfaces of a semiconductor chip 6 are sealed with a potting resin 8, such as an epoxy resin or the like, for preventing the deterioration of the electrical characteristics of the chip 6, which is caused by the intrusion of water content and the like. In a TAB 1, marks M marked a type, a production lot number and the like, for example, are formed on a film 2 at a region where lead wirings 3 are not formed. These marks M are constituted of the same material as that of the wirings 3. That is, the marks M are formed simultaneously in a process, in which a conductive foil (such as a Cu foil) laminated previously on one surface of the film 2 is etched to form the lead wirings 3. The number of manufacturing processes in the TAB can be decreased.