PHASE LOCKED LOOP CIRCUIT

• Main Authors: ITOIGAWA KEIICHI, MIURA KUNIAKI
• Format: Patent
• Language: English
• Published: 19.03.1990
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

PURPOSE:To minimize quantity of noise in a reproduced color signal by controlling the phase of a phase detector in response to the increase/decrease in jitter even if it takes place. CONSTITUTION:A phase locked loop comprising a phase detector 3, a voltage controlled oscillator(VCO) 2, and a frequency multiplier 1 locks the phase between a burst signal of a reproduced color signal 6 being an input signal to the phase detector 3 and a signal of a reference crystal oscillator 4. Then the circuit is provided with a jitter detector 8 detecting a jitter from a reproduced luminance signal 5 and the phase detector 3 whose gain is controlled by an output signal of the jitter detector 8 or the like. If jitter is increased, the quantity of noise changes from a value shown in a curve 12 to a value shown in a curve 14, but since the gain of the phase detector 3 is controlled from h0 to h1 by the detection signal from the jitter detector 8 being the result of detecting the jitter, the noise quantity in the reproduced color signal is minimized.