RECEPTION CLOCK RECOVERY CIRCUIT FOR START-STOP SYNCHRONIZATION DATA

• Main Author: NISHIMURA YASUYO
• Format: Patent
• Language: English
• Published: 02.02.1990
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PURPOSE:To receive a data of the start-stop synchronization system through the use of a general-purpose LSI capable of sending/receiving a continuous synchronizing system data by providing a means recovering a reception clock from the start-stop synchronization system data. CONSTITUTION:When a reception data RD inputted via an interface circuit 1 is fed to a charge point detection circuit 2, the data is sampled by using a clock pulse CLK from a clock generating circuit 4 and a reproduced reception data RD' is obtained. Simultaneously, the change point detection circuit 2 detects a change point of leading and trailing and a change point detection signal VD is given to a reception 1/n frequency divider circuit 6. The frequency divider 6 resets the CLK by using the VD and applies 1/n frequency division and the pulse subject to 1/n frequency division is fed to the general-purpose LSI 3 as a reception clock RC. Thus, the LSI 3 can receive the start-stop synchronization system data correctly by using the clock RC so as to reproduce the data RD'.