STORAGE ADDRESS CONVERSION CONTROL SYSTEM

PURPOSE:To suppress the drop of processing efficiency by converting a logical address into a physical address based upon an address conversion table stored in the 1st address conversion means when the corresponding address conversion table is not stored in the 2nd address conversion means. CONSTITUT...

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Bibliographic Details
Main Author FUJIOKA ISAO
Format Patent
LanguageEnglish
Published 05.12.1990
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To suppress the drop of processing efficiency by converting a logical address into a physical address based upon an address conversion table stored in the 1st address conversion means when the corresponding address conversion table is not stored in the 2nd address conversion means. CONSTITUTION:A logical address calculated by an adder 1 is supplied to both of a storage address conversion reference buffer 2 and a rapid storage address conversion reference buffer 4. When an address conversion table 5a corresponding to the logical address exists, the logical address is immediately converted into a physical address by using the address conversion table 5a and outputted. In the address conversion table corresponding to the logical address does not exist, the logical address is converted into the physical address by an address conversion table read out from the buffer 2 in the succeeding machine cycle. The contents of a main storage cache buffer 3 are read out by the converted physical address. Thus, the drop of the processing efficiency is eliminated.
Bibliography:Application Number: JP19890115506