BUFFER CONTROL SYSTEM

PURPOSE:To simplify the address generating means and to save an ineffective area in a memory by providing a memory which is divided into blocks of plural kinds each of which has the storage capacity of the power of 2. CONSTITUTION:The memory 100 is divided into blocks Ba, Bb of plural kinds each of...

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Bibliographic Details
Main Authors KATO YUJI, HAYAMI SHICHIRO, KAMOI EDAMASU
Format Patent
LanguageEnglish
Published 15.11.1990
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:PURPOSE:To simplify the address generating means and to save an ineffective area in a memory by providing a memory which is divided into blocks of plural kinds each of which has the storage capacity of the power of 2. CONSTITUTION:The memory 100 is divided into blocks Ba, Bb of plural kinds each of which has the storage capacity of the power of 2. A binary counting circuit 200 counts the length of information of the fixed length to be written in or read out of the memory 100, and an address conversion means 300 converts a counted output from the binary counting circuit 200 into the addresses of plural kinds of the blocks Ba, Bb. Thus, it is possible to write and read out set of information into plural kinds of the blocks continuously and since each block has the storage capacity of the power of 2, the memory is utilized effectively. Then plural kinds of blocks are combined so as to minimize the ineffective area to the information of the fixed length and the generation of write and readout address and block idle/occupancy management are simplified, as well.
Bibliography:Application Number: JP19890099331