OUTPUT CIRCUIT FOR DEBUGGING DATA
PURPOSE:To automatically output data written in a certain area on a storage device by transferring data from an address shown in a first comparison address register in the storage device to an address shown in a second comparison address register to an output buffer when a counter has counted out. C...
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Main Author | |
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Format | Patent |
Language | English |
Published |
14.11.1990
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Subjects | |
Online Access | Get full text |
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Summary: | PURPOSE:To automatically output data written in a certain area on a storage device by transferring data from an address shown in a first comparison address register in the storage device to an address shown in a second comparison address register to an output buffer when a counter has counted out. CONSTITUTION:When an execution control part 1 accesses the storage device 2, it outputs the address to an address bus 9. Comparison circuits 5 and 6 respectively compare a value outputted on the address bus 9 with values stored in the comparison address registers 3 and 4. An AND gate 8 outputs a count signal to the counter 10 when coincidence signals from the comparison circuits 5 and 6 come to '1'. A DMA transfer control part 7 DMA-transfers data from the address stored in the comparison address register 3 in the storage device 2 to the address stored in the comparison address register 4 to the output buffer by a count out signal from the counter 10. Thus, data in the storage device can be outputted as for debugging. |
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Bibliography: | Application Number: JP19890100445 |