OPERATING METHOD FOR SOLID-STATE IMAGE PICKUP DEVICE

PURPOSE:To reduce the load capacity and to reduce the power consumption by increasing a low level of a clock signal at the transfer of a charge signal from an image pickup section to a storage section at a high speed more than the low level of the clock signal at signal readout. CONSTITUTION:Buffers...

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Bibliographic Details
Main Author YAMAWAKI MASAO
Format Patent
LanguageEnglish
Published 15.10.1990
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
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Summary:PURPOSE:To reduce the load capacity and to reduce the power consumption by increasing a low level of a clock signal at the transfer of a charge signal from an image pickup section to a storage section at a high speed more than the low level of the clock signal at signal readout. CONSTITUTION:Buffers 61a, 61b capable of setting three states of high level, low level and high impedance states are connected in parallel and its output connects to a clock signal output 66. A signal phiA is given as a clock signal input 65 to an input of the buffers 61a, 61b. A signal phiC switches a level for a period of a vertical blanking period TFT and a signal readout period TRO. Thus, the low level of the clock pulse of the gate at the vertical blanking period at high speed frame transfer is increased more than the low level of the clock pulse for a signal readout period, the load capacity at frame transfer is reduced.
Bibliography:Application Number: JP19890077659