ADDRESS UPDATING CIRCUIT

PURPOSE:To improve a data transfer speed by providing a control means for updating a count value, and at the time of deciding that a specific bit satisfies a prescribed condition, increasing or decreasing the count value only by '1'. CONSTITUTION:A counter 11 outputs a segment address as a...

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Bibliographic Details
Main Author FUKADA TAKASHI
Format Patent
LanguageEnglish
Published 18.09.1990
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To improve a data transfer speed by providing a control means for updating a count value, and at the time of deciding that a specific bit satisfies a prescribed condition, increasing or decreasing the count value only by '1'. CONSTITUTION:A counter 11 outputs a segment address as a count value to form the control means. The upper two bits A14, A15 of an address outputted from a DMAC at the time of data transfer are stored in registers 1, 2, 5, 6. Registers 3, 4, 7, 8 output the contents held in the registers 1, 2, 5, 6 obtained one cycle before to AND gates 9, 10. The gates 9, 10 execute the AND operation between the addresses A14, A15 and the registers 3, 4 or 7, 8. When the output values of the gates 9, 10 are high levels, it is decided that the output values of the holding means and the addresses A14, A15 satisfy the prescribed condition. The control means increases or decreases the count value only by '1' and the segment address is updated by a hardware, so that the data transfer speed can be improved.
Bibliography:Application Number: JP19890054967