OVERLAP PREVENTION SYSTEM FOR LOGICAL PATH ID

PURPOSE:To prevent erroneous connection due to the overlap of a logical path ID by providing an inverted bit in the logical path ID for identifying a logical path in data communication. CONSTITUTION:A logical path ID 20 of a logical path ID control table 10 is a system to constitute a network and is...

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Bibliographic Details
Main Authors OISHI KAZUHIRO, SAGAWA KAZUHIRO
Format Patent
LanguageEnglish
Published 01.08.1990
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:PURPOSE:To prevent erroneous connection due to the overlap of a logical path ID by providing an inverted bit in the logical path ID for identifying a logical path in data communication. CONSTITUTION:A logical path ID 20 of a logical path ID control table 10 is a system to constitute a network and is composed of the ID for identifying a self-process, inverted bit to be inverted to turning-on and off each time the path is interrupted and a series of numbers from 1 to a maximum path number. In a communication program 2, the logical path ID 20 is applied and used as an interface between the programs to realize a protocol. Then, each time the logical path is generated, the idle ID is successively allocated and controlled in a range from 1 to the maximum path number and the inverted bit is set into the ID path, for which the logical path is interrupted by a fault. Thus, the same logical ID path is prevented from being used again for path generation just after the path is interrupted.
Bibliography:Application Number: JP19890014365