VECTOR ARITHMETIC UNIT

PURPOSE:To know an instruction executing with a vector arithmetic unit even when the processing of a central processing unit precedes by providing a flip- flop, a means to hold a software instruction word before one instruction and a means to hold the instruction before one instruction stored into a...

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Bibliographic Details
Main Author SEKIGUCHI ATSUSHI
Format Patent
LanguageEnglish
Published 16.07.1990
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To know an instruction executing with a vector arithmetic unit even when the processing of a central processing unit precedes by providing a flip- flop, a means to hold a software instruction word before one instruction and a means to hold the instruction before one instruction stored into an instruction word register by means of the central processing unit. CONSTITUTION:A CMDI (software instruction backup) resister 13 is the recording register of a software instruction set to a CDM (instruction word) register 10 and backs up only the instruction word set to the CMD register 10 when a signal line 104 is made active. A CMDC (arithmetic instruction backup) register 14 is the register to hold the instruction before one instruction every time the CMD register 10 is updated, a BOPF (software instruction load instructing register) 15 is the flip-flop set by a signal line 103 and reset by the signal line 104, and it indicates to be set as the software instruction word to the CMD register 10. Thus, even when the processing of the central processing unit precedes, the instruction executing by the vector arithmetic unit can be known.
Bibliography:Application Number: JP19890001811