SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PURPOSE:To prevent noise, runaway of a CPU, a etc., from easily causing test mode operation by installing a detector to detect input of voltage higher than source voltage, a detection latch means, and a non-detectin latch means. CONSTITUTION:A detection signal sent from the detection output terminal...

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Bibliographic Details
Main Author UEDA CHIHARU
Format Patent
LanguageEnglish
Published 13.06.1990
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Summary:PURPOSE:To prevent noise, runaway of a CPU, a etc., from easily causing test mode operation by installing a detector to detect input of voltage higher than source voltage, a detection latch means, and a non-detectin latch means. CONSTITUTION:A detection signal sent from the detection output terminal 2a of a detector 2 to detect input of voltage higher than source voltage sent to an input terminal 1 is transmitted to the set input terminal 3a of a detection latch means 3. A non-detection signal sent from a non-detection output terminal 2b is transmitted to the set input terminal 4a of a non-detection latch means 4, output of the non-detection latch means 4 is sent to the reset input terminal 3b of the detection latch means 3, and the reset signal of this system is transmitted to the reset input terminal 4b of the non-detection latch means 4. Thereby input of voltage higher than the source voltage enables test mode operation, however, output of one non-detection signal cancels the test mode operation.
Bibliography:Application Number: JP19880308279