POWER-ON RESET CIRCUIT

PURPOSE:To output a normal reset signal even if a hit takes place by discharging entirely the electric charge in a capacitor through a diode at the release of the reset signal. CONSTITUTION:If a potential of a positive power supply VDD is decreased, that is, a hit takes place in the positive power s...

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Bibliographic Details
Main Author KANO TOSHIYUKI
Format Patent
LanguageEnglish
Published 12.12.1989
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:PURPOSE:To output a normal reset signal even if a hit takes place by discharging entirely the electric charge in a capacitor through a diode at the release of the reset signal. CONSTITUTION:If a potential of a positive power supply VDD is decreased, that is, a hit takes place in the positive power supply, the potential at a node (b) is lowered similarly and the potential at a node (a) is lowered, since the charge of the capacitor 5 is all discharged via a diode 2 at the release of the reset signal, almost no discharge time for the charge is required. When the positive power supply VDD rises again, the circuit state is similar to that at application of power and the reset signal is outputted to an output terminal 7 till the capacitor 5 is sufficiently charged by a resistor 1. Thus, the normal reset signal is outputted even to the decrease in the positive power supply for a short time.
Bibliography:Application Number: JP19880137520