DATA PROCESSOR

PURPOSE:To detect a data error generated at the time of converting word length by providing a means to attach a parity bit on part of converted data according to a remaining part and the parity bit of data to be converted. CONSTITUTION:Assuming that the parity bit 12 is attached on the data 13 to be...

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Bibliographic Details
Main Author KAMEOKA AKIO
Format Patent
LanguageEnglish
Published 08.12.1989
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To detect a data error generated at the time of converting word length by providing a means to attach a parity bit on part of converted data according to a remaining part and the parity bit of data to be converted. CONSTITUTION:Assuming that the parity bit 12 is attached on the data 13 to be converted so as to form odd parity in total, and when (8 bits X 1 word) is converted to (4 bits X 2 words) and it is outputted from a data register 11 to be converted, conversion data is constituted of four high-order bits and four low-order bits, respectively. Those conversion data 18 of four low-order bits and parity bit 12 of the data 13 to be converted are inputted to a parity generation circuit 21, then, the parity bit 37 is attached. And it is sent to a register 20 for conversion data, and the parity bit 37 of the conversion data 17 of four high-order bits forms even parity. Therefore, when an odd number of data errors are generated by conversion, it is possible to detect it as the error at the time of converting the word length.
Bibliography:Application Number: JP19880135807