SEMICONDUCTOR MEMORY

• Main Authors: UJIIE KAZUAKI, FURUSAWA KAZUNORI
• Format: Patent
• Language: English
• Published: 07.11.1989
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PURPOSE:To decrease the number of writings and to shorten a test time by providing a circuit to cause the plural word lines of an array, for which a non-volatile memory element to execute electric writing is matrix-arranged, to be simultaneously in a selecting condition with a prescribed test mode signal. CONSTITUTION:An Nch transmitting gate FET Q3 to receive a test signal TE0 is provided for the output of a decoder G of a unit and a Pch transmitting gate FET Q4 to receive the same signal is provided in an output side. An inverter N3 to receive a test signal TE1 is provided in a word line WL of an even number and an inverter to receive a test signal TE2 is provided in a word line WL of an odd number. The outputs of the inverters go to be a decode output through a correspondent Pch transmitting gate FET Q1. Such a test circuit simultaneously selects the plural word lines WL according to the signals TE0-TE2 without depending on the decode output, namely, an address signal. Thus, since much data can be written by one time of the writing, the test time is shortened. When a signal is inputted from a common terminal with being multiplexed, the test signal is held in a latch circuit FF.