WAIT CONTROL SYSTEM FOR DATA TRANSFER DEVICE

PURPOSE:To freely realize the virtual write/read enable states by controlling the wait of an FIFO. CONSTITUTION:A digital signal processor DSP1 serves as a data transfer device which control the transfer of data based on the empty flag signal (EF) and the full flag signal (FF) of an FIFO memory 2 or...

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Bibliographic Details
Main Authors GOTO TOSHIYUKI, FUJII SHIGERU, MIMA TOSHIYA, YAMAUCHI MITSURU, AIDA KOICHI, TANABE TOMOAKI, OKAMOTO MASAYUKI, KATO KENJI, NAKAYAMA HIROSHI
Format Patent
LanguageEnglish
Published 28.07.1989
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To freely realize the virtual write/read enable states by controlling the wait of an FIFO. CONSTITUTION:A digital signal processor DSP1 serves as a data transfer device which control the transfer of data based on the empty flag signal (EF) and the full flag signal (FF) of an FIFO memory 2 or 3. Then the DSP1 can replace an empty flag EF1 received from the input FIFO memory 2 with a valid or invalid state by a wait signal WAITI through an AND gate and also can update the signal FF1 received from the output FIFO memory 3 by a wait signal WAITO. The types of gates and the valid or invalid state are decided in accordance with each state. Thus the DSP1 can transfer data after reading the EF of FF signal or can transfer data directly without reading the EF nor FF signal.
Bibliography:Application Number: JP19880013122