SEMICONDUCTOR DEVICE

PURPOSE:To reduce production cost by making thin the width of upper-layer wiring of two crossing wires and by forming the lower-layer wiring utilizing horizontal diffusion of impurities diffusion. CONSTITUTION:After a LOCOS 302 is formed on an Si wafer 301, a gate oxide film 303 is formed and then a...

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Bibliographic Details
Main Author YOSHIOKA TATSUROU
Format Patent
LanguageEnglish
Published 26.07.1989
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PURPOSE:To reduce production cost by making thin the width of upper-layer wiring of two crossing wires and by forming the lower-layer wiring utilizing horizontal diffusion of impurities diffusion. CONSTITUTION:After a LOCOS 302 is formed on an Si wafer 301, a gate oxide film 303 is formed and then an upper-layer wiring 304 and a gate electrode 305 are subject to patterning using polysilicon. In this case, the width of a gate electrode 305 should be kept to a dimensional width which does not crush the channel part due to horizontal diffusion of impurities diffusion of post process. Finally, impurities diffusion part 306 formed by normal diffusion of source/ drain constitutes the lower-layer wiring directly below the upper-layer wiring 304 and the channel part of MOS transistor directly below the gate electrode 305. It allows an exclusive process formed by a crossing wiring to be shaped by a totally different process for reducing production cost.
Bibliography:Application Number: JP19880005913