PARTIAL-WRITE CONTROL SYSTEM

PURPOSE:To execute plural partial-writes by the memory access of one time by overwriting new data upon a data holding means when a partial-write operation for the same address is driven in a definite period. CONSTITUTION:When one of banks is started by partial-write access, an array address is given...

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Bibliographic Details
Main Author IKEHARA SHOHEI
Format Patent
LanguageEnglish
Published 22.06.1989
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To execute plural partial-writes by the memory access of one time by overwriting new data upon a data holding means when a partial-write operation for the same address is driven in a definite period. CONSTITUTION:When one of banks is started by partial-write access, an array address is given to an array card 20. On the other hand, a PST-N instruction that the partial-write access is decoded is charged to a pipeline 29, and a bank address to execute the partial-write is charged to the pipeline 31. Besides, write data is inputted to a register 33, and a byte mark is inputted to the register 34. Bank address is written in designated register stacks 21, 22, 23, 24 and 25, 26, 27, 28 according to the bank address respectively decoded. If the partial- write for the same bank exists in a machine cycle 12T, it is overwritten on the register stack respectively.
Bibliography:Application Number: JP19870317575