SEMICONDUCTOR MEMORY DEVICE

PURPOSE:To decrease the number of address decoder circuit elements and internal wiring by providing an address decoder that corresponds to plural memory arrays with plural unit decoders to which address signals less bit in the most significant order in a prescribed combination are supplied as well a...

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Bibliographic Details
Main Author OTA TATSUYUKI
Format Patent
LanguageEnglish
Published 26.04.1989
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To decrease the number of address decoder circuit elements and internal wiring by providing an address decoder that corresponds to plural memory arrays with plural unit decoders to which address signals less bit in the most significant order in a prescribed combination are supplied as well as a common FET that supplies power selectively to the unit decoders in accordance with the address of the most significant bit. CONSTITUTION:The word lines constituting the memory arrays MARY0, MARY1 of a semiconductor memory device are connected to a raw address decoder RDCR to set it in alternate selecting state. This RDCR operates in accordance with a prescribed timing and decodes complementary internal address signals au0-axi to make word lines corresponding to the MARY0, MARY1 to a high level. Also, complementary data lines constituting the MARY0, MARY1 are connected to a switch MOSFET to which column switches CSW0, CSW1 correspond, thereby connected selectively to corresponding complementary common data lines CD0-CD1 via the MOSFET.
Bibliography:Application Number: JP19870266338