JP2980001B

PURPOSE: To extend the total gate width of an FET pallet without restrictions of the width of a package, to realize a high output, to reduce the matching loss due to phase deviation for the extension of the gate width, and to reduce the number of parts. CONSTITUTION: Arrays of gates 2a and drains 2b...

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Bibliographic Details
Main Author ONO FUMINOBU
Format Patent
LanguageEnglish
Published 22.11.1999
Edition6
Subjects
AMPLIFIERS
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
WAVEGUIDES
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Summary:PURPOSE: To extend the total gate width of an FET pallet without restrictions of the width of a package, to realize a high output, to reduce the matching loss due to phase deviation for the extension of the gate width, and to reduce the number of parts. CONSTITUTION: Arrays of gates 2a and drains 2b of an FET pellet 2 are arranged in parallel with the transmission direction of a signal from a gate lead terminal 10 to a drain lead terminal 11. Gates, 2a and drains 2b of the FET pellet 2 are connected to internal matching circuits 5 and 6 in the direction orthogonal to this transmission signal.
Bibliography:Application Number: JP19950160585