JP2978794B

A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at active level, and an internal circuit for, in an ord...

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Bibliographic Details
Main Authors HIKICHI HIROSHI, FUKUHARA YASUSHI
Format Patent
LanguageEnglish
Published 15.11.1999
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder.
Bibliography:Application Number: JP19960296325