JP2853043B

PURPOSE:To synchronize by providing a master clock generating circuit so as to correct deviation between semiconductor memories containing an address generating circuit caused at the asynchronous mode. CONSTITUTION:A semiconductor memory 11 containing an address generating circuit at the asynchronou...

Full description

Saved in:
Bibliographic Details
Main Authors KAWAI HIDEKI, KAGEYAMA YOSHIKAZU, YAMANISHI KAZUHIRO, NAKAYA SHUJI, SAKAGAMI MASAHIKO
Format Patent
LanguageEnglish
Published 03.02.1999
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:PURPOSE:To synchronize by providing a master clock generating circuit so as to correct deviation between semiconductor memories containing an address generating circuit caused at the asynchronous mode. CONSTITUTION:A semiconductor memory 11 containing an address generating circuit at the asynchronous mode has a master clock generating circuit, which generates a master clock when an internal address reaches an optional value. Moreover, storage devices 12, 13 receive the master clock and act like slave operation and set the internal address to an optional value. Even when there is any deviation caused in the internal address of the storage devices 11 to 13 due to distortion of the clock or the like, the slave action is secured to correct deviation and the storage devices 11 to 13 can synchronize by themselves. Furthermore, a circuit generating a signal representing the status of the internal address with a clock output from an external controller 14 is included in the storage devices 11 to 13.
Bibliography:Application Number: JP19890060865