JP2660111B

A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors (Q1 to Q4) and having one end connected to a first node (N1), and a plurality of capacitors (C1 to C4) for data storage connected at one end to the MOS transistors (Q1 to Q4), respectively...

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Bibliographic Details
Main Authors FURUYAMA TOORU, KUSHAMA NATSUKI, TAKASE SATORU
Format Patent
LanguageEnglish
Published 08.10.1997
Edition6
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors (Q1 to Q4) and having one end connected to a first node (N1), and a plurality of capacitors (C1 to C4) for data storage connected at one end to the MOS transistors (Q1 to Q4), respectively, at the end remote from the node (N1), and there is a predetermined regulation in relation of the capacitance of the capacitors.
Bibliography:Application Number: JP19910041321