JP2655441B

A read only semiconductor memory includes a memory cell matrix including a number of floating-gate type erasable programmable memory cells. A column selector being connected between a plurality of column lines of the memory cell matrix and a writing circuit and a sense amplifier. A column decoder ha...

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Bibliographic Details
Main Author OBATA HIROYUKI
Format Patent
LanguageEnglish
Published 17.09.1997
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A read only semiconductor memory includes a memory cell matrix including a number of floating-gate type erasable programmable memory cells. A column selector being connected between a plurality of column lines of the memory cell matrix and a writing circuit and a sense amplifier. A column decoder has a plurality of outputs each being connected through a corresponding transfer gate to the column selector and also being pulled up to a high voltage. A row decoder has a plurality of outputs each being outputted through a corresponding transfer gate to a corresponding one of row lines of memory cell matrix and also being pulled up to a high voltage to the outputs of the row decoder. Each of the transfer gates is formed of an enhancement type or a substrate-VT type field effect transistor. A control circuit including a pump-up circuit receives a control signal for supplying a gate voltage signal to gates of all the field effect transistors.
Bibliography:Application Number: JP19900186042