JP2559556B

PURPOSE:To improve the degree of integration while keeping a high speed by interposing a bipolar transistor TR between parts of heavy load out of parts connected to a bus. CONSTITUTION:A PNP TR and an NPN TR are complementarily connected in the output of a MOB buffer 40. Plural pairs of TRs are inpu...

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Bibliographic Details
Main Authors MASUDA IKURO, MAEJIMA HIDEO
Format Patent
LanguageEnglish
Published 04.12.1996
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PURPOSE:To improve the degree of integration while keeping a high speed by interposing a bipolar transistor TR between parts of heavy load out of parts connected to a bus. CONSTITUTION:A PNP TR and an NPN TR are complementarily connected in the output of a MOB buffer 40. Plural pairs of TRs are inputted to a bipolar buffer 41. This bipolar buffer 41 is a coupling circuit interposed between a logic block (MOB buffer 40) and another logic block (MOS address decoder 42) and amplifies the current of the output of the MOS buffer 40 to powerfully drive the MOS address decoder 42 in the next stage. Consequently, the signal from the MOS buffer 40 is quickly transmitted to the MOS address decoder 42 by passing the bipolar buffer 41 though the degree of integration of the MOS address decoder 42 in the next stage is high.
Bibliography:Application Number: JP19930003849