JP2558931B

The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer (102, 103) doped with an impurity and a refractory metal silicide layer (104) has an impurity concentration that is reduced c...

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Bibliographic Details
Main Author SHINO KATSUYA
Format Patent
LanguageEnglish
Published 27.11.1996
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer (102, 103) doped with an impurity and a refractory metal silicide layer (104) has an impurity concentration that is reduced close to a boundary between the polysilicon layer and the refractory metal silicide layer. With this structure, the difference in oxidation speed between the polysilicon layer and the silicide layer is smaller in comparison with a conventional structure, and thus peeling due to bird's beaks can be prevented. The semiconductor device of this structure can be realized by a two-layer polysilicon structure (102, 103) in which the upper layer in contact with the refractory metal silicide layer has a lower impurity concentration, or by a structure in which the peak of the impurity concentration profile is set to be deep within the polysilicon layer during ion implantation.
Bibliography:Application Number: JP19900185604