JP2534786B

• Main Authors: MATSUMOTO NAOKI, WATANABE JUJI, OOSHIMA SHIGEO
• Format: Patent
• Language: English
• Published: 18.09.1996
• Edition: 6
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A semiconductor memory device including: a data storage device (M) having a plurality of memory cells (MC) each capable of storing a data and being selected by an address (Ai), first complementary data corresponding to the data in a selected memory cell being outputted to first complementary data lines (DQ, DQ); a first equalizer (Tel) for short-circuiting and equalizing the first complementary data lines (DQ, DQ); an amplifier (A) for receiving the first complementary data from the first complementary data lines (DQ, DQ), making large the difference between levels of the first complementary data, and outputting as second complementary data the levels to second complementary data lines (RD1, RD1); a second equalizer (Te2) for short-circuiting and equalizing the second complementary data lines (RD1, RD1); a data latch circuit (B) having latch units (DH1, DH2) and switching means (IB1, IB2), the latch unit receiving and latching the second complementary data from the second complementary data lines (RD1, RD1) and outputting as third complementary data the second complementary data to third complementary data lines (RD2, RD2), the switching unit connecting/disconnecting the second complementary data lines (RD1, RD1), and the switching unit being serially connected to the second complementary data lines (RD1, RD1) between the second equalizer (Te2) and the latch units (DH1, DH2); and an output unit (C) for receiving the third complementary data from the third complementary data lines (RD2, RD2) and outputting an output signal corresponding to the third complementary data.