JP2522068B

• Main Author: DAIHO MASAHIRO
• Format: Patent
• Language: English
• Published: 07.08.1996
• Edition: 6
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

PURPOSE:To sample only an effective signal voltage accurately even when a clock rate of a CCD gets higher by obtaining a potential difference between a potential of a feed-through period and a potential of a signal period with a simple circuit comprising a delay line and a buffer circuit without clamping. CONSTITUTION:The potential difference between a potential of a feedthrough period and a potential of a signal period is obtained through the use of the refection of a delay line 13 and no clamping is required, the unit is stable even when multi picture element and high speed configuration is adopted for a CCD (charge coupled device) 1. A sample-and-hold circuit providing the integration characteristic with a CR (C: holding capacitor 10 and R is resistor 12) for an effective signal voltage is used for the sampling. Since the response against a high frequency noise component is suppressed by the integration characteristic, the loopback component into the band with sampling is reduced. Thus, the unit is stable for the high speed operation and the loopback noise component is reduced.