MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• Main Authors: OGURA RYO, MARUYAMA TAKAHIRO, SATO MASAYUKI
• Format: Patent
• Language: English; Japanese
• Published: 27.06.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To suppress the generation of foreign matter.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: forming gate trenches GTR1, GTR2, and GTR of transistors; forming a polysilicon film PSF on the upper surface of a semiconductor substrate SUB including the inside of the gate trenches GTR1, GTR2, and GTR; and performing an etch-back process on the polysilicon film PSF. Here, an "improved recess LOCOS" 200, which is a field insulating film includes a bird's beak portion 51, a bird's head portion 52 connected to the bird's beak portion 51, and a flat portion 53 connected to the bird's head portion 52. The step of performing the etch-back process on the polysilicon film PSF is performed in a state in which the flat portion 53 is located lower than an upper surface US of the semiconductor substrate SUB, and after this step, a residue 80 composed of a part of the polysilicon film PSF remains at the connection portion between the bird's head portion 52 and the flat portion 53.SELECTED DRAWING: Figure 24 【課題】異物の発生を抑制する。【解決手段】半導体装置の製造方法は、トランジスタのゲートトレンチＧＴＲ１、ＧＴＲ２、ＧＴＲを形成する工程と、ゲートトレンチＧＴＲ１、ＧＴＲ２、ＧＴＲの内部を含む半導体基板ＳＵＢの上面上にポリシリコン膜ＰＳＦを形成する工程と、ポリシリコン膜ＰＳＦに対してエッチバック処理を施す工程を備える。ここで、フィールド絶縁膜である「改良型リセスＬＯＣＯＳ」２００は、バーズビーク部５１と、バーズビーク部５１と繋がるバーズヘッド部５２と、バーズヘッド部５２と繋がる平坦部５３とを有する。ポリシリコン膜ＰＳＦに対してエッチバック処理を施す工程は、平坦部５３が半導体基板ＳＵＢの上面ＵＳよりも低い位置にある状態で実施され、この工程の後、バーズヘッド部５２と平坦部５３との接続部位にポリシリコン膜ＰＳＦの一部から構成される残渣８０が残存する。【選択図】図２４