RECEIVER CIRCUIT AND OPTICAL RECEIVER CIRCUIT
To reduce fluctuation in frequency characteristic at changing the gain.SOLUTION: A receiver circuit includes: a constant current circuit for generating a second differential current signal according to a first differential current signal; a current divider circuit for outputting a third differential...
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Main Authors | , , |
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Format | Patent |
Language | English Japanese |
Published |
20.06.2024
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Subjects | |
Online Access | Get full text |
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Summary: | To reduce fluctuation in frequency characteristic at changing the gain.SOLUTION: A receiver circuit includes: a constant current circuit for generating a second differential current signal according to a first differential current signal; a current divider circuit for outputting a third differential current signal generated from the second differential current signal from a first output node and a second output node; and a differential TIA circuit for outputting a differential voltage signal from a first output terminal and a second output terminal according to the third differential current signal inputted from a third input node and a fourth input node. The differential TIA circuit includes: a first feedback resistance element connected between the third input node and the second output terminal; and a second feedback resistance element connected between the fourth input node and the first output terminal. Average voltages at the first output node, the second output node, the first output terminal, and the second output terminal is set to be mutually equal.SELECTED DRAWING: Figure 2
【課題】利得を変化させる際の周波数特性の変動を低減すること。【解決手段】第1差動電流信号に応じて第2差動電流信号を生成する定電流回路と、前記第2差動電流信号から生成した第3差動電流信号を第1出力ノードおよび第2出力ノードから出力する電流分流回路と、第3入力ノードおよび第4入力ノードから入力される前記第3差動電流信号に応じて差動電圧信号を第1出力端子および第2出力端子から出力する差動TIA回路と、を備え、差動TIA回路は、第3入力ノードと第2出力端子との間に接続される第1帰還抵抗素子と、第4入力ノードと第1出力端子との間に接続される第2帰還抵抗素子と、を備え、前記第1出力ノード、前記第2出力ノード、前記第1出力端子および前記第2出力端子のそれぞれの平均電圧は、互いに等しくなるように設定されている、受信回路。【選択図】図2 |
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Bibliography: | Application Number: JP20220196049 |