SEMICONDUCTOR DEVICE
To propose a storage device capable of increasing storage capacity per unit area while ensuring a data retention period.SOLUTION: In a semiconductor device: a plurality of bit lines are divided into some groups and a plurality of word lines are also divided into some groups; and to memory cells conn...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
23.04.2024
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Subjects | |
Online Access | Get full text |
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Summary: | To propose a storage device capable of increasing storage capacity per unit area while ensuring a data retention period.SOLUTION: In a semiconductor device: a plurality of bit lines are divided into some groups and a plurality of word lines are also divided into some groups; and to memory cells connected to the bit lines belonging to one group, the word lines belonging to one group are connected; and further, the plurality of bit lines are controlled to be driven with respect to each group by a plurality of bit line drive circuits; and in addition, on drive circuits including the plurality of bit line drive circuits and the word line drive circuit, a cell array is formed. By stacking the drive circuits and the cell array in an overlapping manner to form a three dimensional stacking, an occupied area of a storage device can be reduced though a plurality of bit line drive circuits are provided.SELECTED DRAWING: Figure 1
【課題】データの保持期間を確保しつつ、単位面積あたりの記憶容量を高めることができる記憶装置の提案すること。【解決手段】複数のビット線を幾つかのグループに分割し、複数のワード線も幾つかのグループに分割する。そして、一のグループに属するビット線に接続されたメモリセルには、一のグループに属するワード線が接続されるようにする。さらに、上記複数のビット線は、複数のビット線駆動回路によってグループごとにその駆動が制御されるようにする。加えて、上記複数のビット線駆動回路と、ワード線駆動回路とを含めた駆動回路上に、セルアレイを形成する。駆動回路とセルアレイが重なるように三次元化することで、ビット線駆動回路が複数設けられていても、記憶装置の占有面積を小さくすることができる。【選択図】図1 |
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Bibliography: | Application Number: JP20240028716 |