MEMORY DEVICE

• Main Author: MINEMURA YOICHI
• Format: Patent
• Language: English; Japanese
• Published: 27.03.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To improve reliability of a memory device.SOLUTION: A memory device comprises: a plurality of insulator layers which are aligned to be spaced away from one another in a first direction; a plurality of conductor layers which are aligned to be spaced away from one another in the first direction via the plurality of insulator layers; and a memory pillar which extends in the first direction in a manner intersecting the plurality of conductor layers. The plurality of conductor layers include a first conductor layer which has a first portion and a second portion aligned in the first direction at a boundary with the memory pillar. With respect to the second portion, the first portion retreats in a second direction which intersects the first direction, and in which a memory pillar diameter increases. The plurality of insulator layers include: a first insulator layer which is provided on a surface of the first conductor layer on the first portion side; and a second insulator layer which is provided on a surface of the first conductor layer on the second portion side, and which is thinner than the first insulator layer in the first direction.SELECTED DRAWING: Figure 7 【課題】メモリデバイスの信頼性を向上させる。【解決手段】一実施形態のメモリデバイスは、第１方向に互いに離れて並ぶ複数の絶縁体層と、複数の絶縁体層を介して第１方向に互いに離れて並ぶ複数の導電体層と、複数の導電体層と交差するように第１方向に延びるメモリピラーと、を備える。複数の導電体層は、メモリピラーとの境界で第１方向に並ぶ第１部分及び第２部分を有する第１導電体層を含む。第１部分は、第２部分に対して、第１方向と交差しかつメモリピラーの径が増加する第２方向に後退する。複数の絶縁体層は、第１導電体層の第１部分側の面上に設けられる第１絶縁体層と、第１導電体層の第２部分側の面上に設けられ、第１方向に第１絶縁体層より薄い第２絶縁体層と、を含む。【選択図】図７