SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• Main Authors: NOGUCHI SEISHI, SAKURAI YOSUKE, YAMADA TAKUYA, HAMAZAKI RYUTARO, SUGANUMA NAO
• Format: Patent
• Language: English; Japanese
• Published: 13.03.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor device capable of reducing an on-voltage by increasing doping concentration of an N+ type storage region and a carrier injection promotion effect, and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device 100 comprises a transistor part 70. The transistor part comprises a drift region 18 of a first conductivity type provided on a semiconductor substrate 10, a base region 14 of a second conductivity type provided above the drift region, a storage region 16 of the first conductivity type provided above the drift region, a plurality of trench parts (dummy trench part 30, gate trench part 40) provided extending from a front surface of the semiconductor substrate to the drift region, and a trench bottom part 75 of the second conductivity type provided in bottoms of the plurality of trench parts. The storage region contains doping concentration whose half value width is 0.3 μm or above.SELECTED DRAWING: Figure 2A 【課題】Ｎ＋型の蓄積領域のドーピング濃度を高め、キャリアの注入促進効果を高めてオン電圧を低減した半導体装置および半導体装置の製造方法を提供する。【解決手段】トランジスタ部７０を備える半導体装置１００であって、トランジスタ部は、半導体基板１０に設けられた第１導電型のドリフト領域１８と、ドリフト領域の上方に設けられた第２導電型のベース領域１４と、ドリフト領域よりも上方に設けられた第１導電型の蓄積領域１６と、半導体基板のおもて面からドリフト領域まで延伸して設けられた複数のトレンチ部（ダミートレンチ部３０、ゲートトレンチ部４０）と、複数のトレンチ部の底部に設けられた第２導電型のトレンチボトム部７５とを有する、蓄積領域は、半値幅が０．３μｍ以上のドーピング濃度を有する。【選択図】図２Ａ