SEMICONDUCTOR DEVICE
To provide a semiconductor device capable of suppressing migration to tipping formed during dicing.SOLUTION: A semiconductor device 100 includes a plurality of transistors. The semiconductor device 100 includes: a substrate 10 having a main surface 10a; an interlayer insulation film 20 disposed on t...
Saved in:
Main Author | |
---|---|
Format | Patent |
Language | English Japanese |
Published |
28.02.2024
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | To provide a semiconductor device capable of suppressing migration to tipping formed during dicing.SOLUTION: A semiconductor device 100 includes a plurality of transistors. The semiconductor device 100 includes: a substrate 10 having a main surface 10a; an interlayer insulation film 20 disposed on the main surface 10a; and a seal ring 40. The seal ring 40 includes an annular portion 41 and a connecting portion 42. The annular portion is disposed on an outer peripheral edge portion of the interlayer insulating film 20 in a plan view and being an annular shape in a plan view. The connecting portion is embedded in the interlayer insulating film 20 and connects the annular portion 41 and the main surface 10a. A minimum value of a gate length L of the plurality of transistors is 0.6 μm or more.SELECTED DRAWING: Figure 2
【課題】ダイシングの際に形成されるチッピングへのマイグレーションを抑制可能な半導体装置を提供する。【解決手段】半導体装置100は、複数のトランジスタを有している。半導体装置100は、主面10aを有する半導体基板10と、主面10a上に配置されている層間絶縁膜20と、シールリング40とを備えている。シールリング40は、平面視における層間絶縁膜20の外周縁部上に配置され、かつ平面視において環状の環状部41と、層間絶縁膜20中に埋め込まれ、かつ環状部41及び主面10aを接続している接続部42とを有している。複数のトランジスタについてのゲート長Lの最小値は、0.6μm以上である。【選択図】図2 |
---|---|
AbstractList | To provide a semiconductor device capable of suppressing migration to tipping formed during dicing.SOLUTION: A semiconductor device 100 includes a plurality of transistors. The semiconductor device 100 includes: a substrate 10 having a main surface 10a; an interlayer insulation film 20 disposed on the main surface 10a; and a seal ring 40. The seal ring 40 includes an annular portion 41 and a connecting portion 42. The annular portion is disposed on an outer peripheral edge portion of the interlayer insulating film 20 in a plan view and being an annular shape in a plan view. The connecting portion is embedded in the interlayer insulating film 20 and connects the annular portion 41 and the main surface 10a. A minimum value of a gate length L of the plurality of transistors is 0.6 μm or more.SELECTED DRAWING: Figure 2
【課題】ダイシングの際に形成されるチッピングへのマイグレーションを抑制可能な半導体装置を提供する。【解決手段】半導体装置100は、複数のトランジスタを有している。半導体装置100は、主面10aを有する半導体基板10と、主面10a上に配置されている層間絶縁膜20と、シールリング40とを備えている。シールリング40は、平面視における層間絶縁膜20の外周縁部上に配置され、かつ平面視において環状の環状部41と、層間絶縁膜20中に埋め込まれ、かつ環状部41及び主面10aを接続している接続部42とを有している。複数のトランジスタについてのゲート長Lの最小値は、0.6μm以上である。【選択図】図2 |
Author | NAKAYA GORO |
Author_xml | – fullname: NAKAYA GORO |
BookMark | eNrjYmDJy89L5WQQCXb19XT293MJdQ7xD1JwcQ3zdHblYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBkYmBkamFpbmjsZEKQIAiC8g6g |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | 半導体装置 |
ExternalDocumentID | JP2024025897A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_JP2024025897A3 |
IEDL.DBID | EVB |
IngestDate | Fri Aug 30 05:40:26 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English Japanese |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_JP2024025897A3 |
Notes | Application Number: JP20220129251 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240228&DB=EPODOC&CC=JP&NR=2024025897A |
ParticipantIDs | epo_espacenet_JP2024025897A |
PublicationCentury | 2000 |
PublicationDate | 20240228 |
PublicationDateYYYYMMDD | 2024-02-28 |
PublicationDate_xml | – month: 02 year: 2024 text: 20240228 day: 28 |
PublicationDecade | 2020 |
PublicationYear | 2024 |
RelatedCompanies | ROHM CO LTD |
RelatedCompanies_xml | – name: ROHM CO LTD |
Score | 3.6597877 |
Snippet | To provide a semiconductor device capable of suppressing migration to tipping formed during dicing.SOLUTION: A semiconductor device 100 includes a plurality of... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | SEMICONDUCTOR DEVICE |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240228&DB=EPODOC&locale=&CC=JP&NR=2024025897A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQMQc2sS2Sjc10gY0HY12TtFQz3UQzkxRdI3PzxKQk46Rkw0TQfmdfPzOPUBOvCNMIJoZs2F4Y8Dmh5eDDEYE5KhmY30vA5XUBYhDLBby2slg_KRMolG_vFmLrogbtHYOmCows1FycbF0D_F38ndWcnW29AtT8gqByphaW5o7MDKzAdrQ5uNcW5gTallKAXKe4CTKwBQCNyysRYmDKShRm4HSGXb0mzMDhC53xBjKhma9YhEEkGBRm_n4uoc4h_kEKLq5hns6uogxKbq4hzh66QOPj4Z6J9wpAcoqxGAMLsJefKsGgYJxskGxukGxhmWpgAqwwki3TUkADDMD2SYqhKbCRIckgjccgKbyy0gxcIB5kJ7YMA0tJUWmqLLAuLUmSA4cBAPgpc60 |
link.rule.ids | 230,309,783,888,25577,76883 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQMQc2sS2Sjc10gY0HY12TtFQz3UQzkxRdI3PzxKQk46Rkw0TQfmdfPzOPUBOvCNMIJoZs2F4Y8Dmh5eDDEYE5KhmY30vA5XUBYhDLBby2slg_KRMolG_vFmLrogbtHYOmCows1FycbF0D_F38ndWcnW29AtT8gqByphaW5o7MDKzANrYFuK8U5gTallKAXKe4CTKwBQCNyysRYmDKShRm4HSGXb0mzMDhC53xBjKhma9YhEEkGBRm_n4uoc4h_kEKLq5hns6uogxKbq4hzh66QOPj4Z6J9wpAcoqxGAMLsJefKsGgYJxskGxukGxhmWpgAqwwki3TUkADDMD2SYqhKbCRIckgjccgKbyy8gycHiG-PvE-nn7e0gxcIBnIrmwZBpaSotJUWWC9WpIkBw4PAIvddp0 |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=SEMICONDUCTOR+DEVICE&rft.inventor=NAKAYA+GORO&rft.date=2024-02-28&rft.externalDBID=A&rft.externalDocID=JP2024025897A |