SEMICONDUCTOR DEVICE

To provide a semiconductor device capable of suppressing migration to tipping formed during dicing.SOLUTION: A semiconductor device 100 includes a plurality of transistors. The semiconductor device 100 includes: a substrate 10 having a main surface 10a; an interlayer insulation film 20 disposed on t...

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Bibliographic Details
Main Author NAKAYA GORO
Format Patent
LanguageEnglish
Japanese
Published 28.02.2024
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:To provide a semiconductor device capable of suppressing migration to tipping formed during dicing.SOLUTION: A semiconductor device 100 includes a plurality of transistors. The semiconductor device 100 includes: a substrate 10 having a main surface 10a; an interlayer insulation film 20 disposed on the main surface 10a; and a seal ring 40. The seal ring 40 includes an annular portion 41 and a connecting portion 42. The annular portion is disposed on an outer peripheral edge portion of the interlayer insulating film 20 in a plan view and being an annular shape in a plan view. The connecting portion is embedded in the interlayer insulating film 20 and connects the annular portion 41 and the main surface 10a. A minimum value of a gate length L of the plurality of transistors is 0.6 μm or more.SELECTED DRAWING: Figure 2 【課題】ダイシングの際に形成されるチッピングへのマイグレーションを抑制可能な半導体装置を提供する。【解決手段】半導体装置１００は、複数のトランジスタを有している。半導体装置１００は、主面１０ａを有する半導体基板１０と、主面１０ａ上に配置されている層間絶縁膜２０と、シールリング４０とを備えている。シールリング４０は、平面視における層間絶縁膜２０の外周縁部上に配置され、かつ平面視において環状の環状部４１と、層間絶縁膜２０中に埋め込まれ、かつ環状部４１及び主面１０ａを接続している接続部４２とを有している。複数のトランジスタについてのゲート長Ｌの最小値は、０．６μｍ以上である。【選択図】図２
Bibliography:Application Number: JP20220129251