SOLID-STATE IMAGING ELEMENT AND METHOD FOR MANUFACTURING THE SAME
To provide a solid-state imaging element, capable of increasing the channel area of a pixel transistor and reducing the parasitic capacitance of a gate.SOLUTION: A solid-state imaging element including a pixel for performing photoelectric conversion includes: a substrate on which the pixel is provid...
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Main Authors | , , , , , , , |
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Format | Patent |
Language | English Japanese |
Published |
07.02.2024
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a solid-state imaging element, capable of increasing the channel area of a pixel transistor and reducing the parasitic capacitance of a gate.SOLUTION: A solid-state imaging element including a pixel for performing photoelectric conversion includes: a substrate on which the pixel is provided: a first transistor including a first gate electrode part which is provided in the pixel and which is embedded in a first direction oriented from a first surface of the substrate toward a second surface of the substrate on the opposite side to the first surface; a first gate insulating film provided between an active region of the substrate in which the channel of the first transistor is formed, and a first side surface of the first gate electrode part facing the active region; and a first insulating film which is provided on a second side surface of the first gate electrode part other than the first side surface and which is thicker than the first gate insulating film. The depth of the first insulating film from the first surface toward the second surface of the substrate is substantially the same as or greater than the depth of the first gate electrode part, and in a cross section in the first direction, the width of an upper surface of the first gate electrode part is greater than the width of a bottom surface of the first gate electrode part.SELECTED DRAWING: Figure 4A
【課題】画素トランジスタのチャネル面積を増大させ、ゲートの寄生容量を低減可能な固体撮像素子を提供する。【解決手段】固体撮像素子は、光電変換する画素を備えた固体撮像素子であり、画素が設けられた基板と、画素に設けられ基板の第1面から第1面に対して反対側の基板の第2面へ向かう第1方向に埋め込まれた第1ゲート電極部分を備える第1トランジスタと、基板のうち第1トランジスタのチャネルが形成される活性領域と該活性領域に対向する第1ゲート電極部分の第1側面との間に設けられた第1ゲート絶縁膜と、第1側面以外の第1ゲート電極部分の第2側面に設けられ、第1ゲート絶縁膜よりも厚い第1絶縁膜とを備え、基板の第1面から第2面への第1絶縁膜の深さは、第1ゲート電極部分の深さとほぼ同じかあるいはそれより深く、第1方向の断面において、第1ゲート電極部分の上面の幅は、該第1ゲート電極部分の底面の幅よりも広い。【選択図】図4A |
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Bibliography: | Application Number: JP20200212372 |