SOLID-STATE IMAGING DEVICE

To provide an imaging device which enables the characteristics of pixel transistors to be adjusted and can be miniaturized.SOLUTION: In a solid-state imaging device including a plurality of pixels provided on the surface of a substrate, the pixel includes a photoelectric conversion portion, a first...

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Bibliographic Details
Main Author KIMIZUKA NAOHIKO
Format Patent
LanguageEnglish
Japanese
Published 16.01.2024
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Summary:To provide an imaging device which enables the characteristics of pixel transistors to be adjusted and can be miniaturized.SOLUTION: In a solid-state imaging device including a plurality of pixels provided on the surface of a substrate, the pixel includes a photoelectric conversion portion, a first transistor whose one end is connected to the photoelectric conversion portion, a second transistor provided between a first power supply and a first signal line, and a third transistor connected between the second transistor and the first signal line. The second transistor includes a first channel region extending substantially vertically to the surface of the substrate, and a first gate electrode which is provided on the top surface and both side surfaces of the first channel region and connected to the other end of the first transistor. The third transistor has a second channel region extending substantially vertically to the surface of the substrate, and a second gate electrode which is provided on the top surface and both side surfaces of the second channel region. A first width between both side surfaces of the first channel region and a second width between both side surfaces of the second channel region are different from each other.SELECTED DRAWING: Figure 5A 【課題】画素トランジスタの特性を調整でき、微細化できる撮像素子を提供する。【解決手段】固体撮像素子は基板の表面上に設けられた複数の画素を備えた固体撮像素子であって、画素は、光電変換部と、光電変換部に一端が接続された第1トランジスタと、第1電源と第1信号線との間に設けられた第2トランジスタと、第2トランジスタと第1信号線との間に接続された第3トランジスタとを備え、第2トランジスタは、基板の表面に対して略垂直方向へ延伸する第1チャネル領域と、第1チャネル領域の上面および両側面に設けられ、第1トランジスタの他端に接続された第1ゲート電極とを有し、第3トランジスタは、基板の表面に対して略垂直方向へ延伸する第2チャネル領域と、第2チャネル領域の上面および両側面に設けられた第2ゲート電極とを有し、第1チャネル領域の両側面間の第1幅と第2チャネル領域の両側面間の第2幅とは互いに異なる。【選択図】図5A
Bibliography:Application Number: JP20200202204