SEMICONDUCTOR DEVICE
To provide a semiconductor device that is mounted with a snubber circuit, and that can suppress reduction in reliability of a power semiconductor element due to heat generation and reduction in snubber effect accompanying longer wiring, respectively.SOLUTION: A semiconductor device comprises: an ins...
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Main Authors | , , |
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Format | Patent |
Language | English Japanese |
Published |
27.12.2023
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a semiconductor device that is mounted with a snubber circuit, and that can suppress reduction in reliability of a power semiconductor element due to heat generation and reduction in snubber effect accompanying longer wiring, respectively.SOLUTION: A semiconductor device comprises: an insulation circuit board; semiconductor chips 3a to 3d arranged on the insulation circuit board; a first external connection terminal 22 arranged on the insulation circuit board; a relay terminal 81 arranged on the insulation circuit board; a printed board 6 arranged over the semiconductor chips 3a to 3d, and connected to the first external connection terminal 22 and relay terminal 81; and snubber circuits (82a and 82b, 83a and 83b) arranged on the printed board 6, and each having one end connected to the first external connection terminal 22 through the printed board 6 and the other end connected to the relay terminal 81 through the printed board 6.SELECTED DRAWING: Figure 7
【課題】スナバ回路を搭載した半導体装置において、パワー半導体素子の発熱による信頼性の低減、及び長配線化に伴うスナバ効果の低減をそれぞれ抑制することができる半導体装置を提供する。【解決手段】絶縁回路基板と、絶縁回路基板上に配置された半導体チップ3a~3dと、絶縁回路基板上に配置された第1外部接続端子22と、絶縁回路基板上に配置された中継端子81と、半導体チップ3a~3dの上方に配置され、第1外部接続端子22及び中継端子81に接続されたプリント基板6と、プリント基板6上に配置され、プリント基板6を介して第1外部接続端子22に一端が接続され、プリント基板6を介して中継端子81に他端が接続されたスナバ回路(82a,82b,83a,83b)とを備える。【選択図】図7 |
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Bibliography: | Application Number: JP20220096388 |