IMAGING ELEMENT

• Main Authors: KITAMURA KAZUYA, YAMASHITA TAKAYUKI, KIKUCHI YUKIHIRO, TOMIOKA KOHEI, YASUE TOSHIO, NAKAMURA TOMOHIRO
• Format: Patent
• Language: English; Japanese
• Published: 07.12.2023
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

To control two elements of spatial resolution and time resolution more in detail while decreasing the number of transistors added to one common pixel structure to one.SOLUTION: An imaging element is based upon a 4-transistor type, and each common pixel structure 10 is provided with one transfer gate control transistor (hereinafter, TGC), and the TGC has its gate connected to one of a transfer timing signal line and a transfer gate control signal line, and one of its source and drain connected to the other of the transfer timing signal line and transfer gate control signal line and the other connected to the gate of each gate transistor (hereinafter TG), where the number of common pixel structure included in each control unit is N and the number of TGs that each common pixel structure has is N, a TGC provided for each common pixel structure being connected to the gate terminal of one TG made to correspond to the TGC among N TGs provided for the common pixel structure to drive the TG.SELECTED DRAWING: Figure 1 【課題】 共有画素構造１つあたりに追加するトランジスタを１個に抑制しつつ、空間解像度と時間解像度の２つの要素をより細かく制御可能とする。【解決手段】 ４トランジスタ型をベースとし、共有画素構造１０の各々に、１つの転送ゲート制御トランジスタ（以下、TGC）を設け、TGCは、ゲートを、転送タイミング信号線および転送ゲート制御信号線の一方に接続し、ソース/ドレインの一方を、転送タイミング信号線および転送ゲート制御信号線の他方に接続し、ソース/ドレインの他方を、各転送ゲートトランジスタ（以下、TG）のゲートに接続し、各制御単位に含まれる共有画素構造の数をN、各共有画素構造が有するTGの数をNとし、各共有画素構造に１つ設けられたTGCは、各共有画素構造に設けられたN個のTGのうち、当該TGCと対応付けられた１つのTGのゲート端子の各々と接続され、当該TGを駆動する。【選択図】図１