SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• Main Author: YUN JONG MIN
• Format: Patent
• Language: English; Japanese
• Published: 01.12.2023
• Subjects: ELECTRICITY

To provide a semiconductor device and a manufacturing method thereof in which an electrode layer around a variable resistance layer is formed from a metal-insulator transition (TDMIT) material that exhibits different resistance depending on its thickness, and during patterning, by using a material in which atoms in the TDMIT material are redeposited on the sidewalls of the variable resistance layer as a sidewall protective layer, SFR due to a detour current is lowered, and several IBE steps to remove redeposited materials and sidewall steps to protect the variable resistance layer can be largely omitted.SOLUTION: A semiconductor device includes a first wiring 110 on a substrate 100, a second wiring 130 arranged above the first wiring at a distance from the first wiring, and a memory cell 120 including a variable resistance layer 124 disposed between the first and second wiring, a sidewall protection layer 125 including a TDMIT material, electrode layers 121, 123, and 126 that are disposed between the first wiring and the variable resistance layer or between the variable resistance layer and the second wiring, and that include the TDMIT material that exhibits different resistance depending on its thickness. and a selective element layer 122.SELECTED DRAWING: Figure 1B 【課題】可変抵抗層周辺の電極層を厚みによって異なる抵抗を表す金属－絶縁体転移（ＴＤＭＩＴ）物質で形成し、パターニングの際、ＴＤＭＩＴ物質内の原子が可変抵抗層側壁に再蒸着された物質を側壁保護層として用いることで、迂回電流によるＳＦＲを低め、再蒸着された物質を除去するための数回のＩＢＥ及び可変抵抗層保護のための側壁工程を相当部分省略できる半導体装置及びその製造方法を提供する。【解決手段】半導体装置は、基板１００上の第１の配線１１０と、その上に第１の配線と離間して配置される第２の配線１３０と、第１、第２の配線の間に配置される可変抵抗層１２４、ＴＤＭＩＴ物質を含む側壁保護層１２５、第１の配線と可変抵抗層との間又は可変抵抗層と第２の配線との間のうち何れかに配置され、厚みによって異なる抵抗を表すＴＤＭＩＴ物質を含む電極層１２１、１２３、１２６及び選択素子層１２２からなるメモリセル１２０と、を備える。【選択図】図１Ｂ