WAFER MOUNTING TABLE
To suppress the occurrence of temperature singularities in a vicinity directly above a terminal hole on a wafer.SOLUTION: A wafer mounting table 10 includes a ceramic substrate 20, a cooling substrate 30, a power supply terminal 54, and a power supply terminal hole 36. The ceramic substrate 20 has a...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
08.11.2023
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Subjects | |
Online Access | Get full text |
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Summary: | To suppress the occurrence of temperature singularities in a vicinity directly above a terminal hole on a wafer.SOLUTION: A wafer mounting table 10 includes a ceramic substrate 20, a cooling substrate 30, a power supply terminal 54, and a power supply terminal hole 36. The ceramic substrate 20 has a wafer mounting surface 22a on the top surface, and incorporates an electrode 26 therein. The cooling substrate 30 is joined to the bottom surface of the ceramic substrate 20, and a coolant passage 32 is formed in the cooling substrate. The power supply terminal 54 is connected to the electrode 26. The power supply terminal hole 36 penetrates through the cooling substrate 30 in a vertical direction and houses the power supply terminal 54 therein. The power supply terminal hole 36 intersects the coolant passage 32.SELECTED DRAWING: Figure 1
【課題】ウエハのうち端子穴の直上付近が温度特異点になるのを抑制する。【解決手段】ウエハ載置台10は、セラミック基材20と、冷却基材30と、給電端子54と、給電端子穴36とを備える。セラミック基材20は、上面にウエハ載置面22aを有し、電極26を内蔵する。冷却基材30は、セラミック基材20の下面に接合され、冷媒流路32が形成されている。給電端子54は、電極26に接続されている。給電端子穴36は、冷却基材30を上下方向に貫通し、給電端子54を収納する。給電端子穴36は、冷媒流路32と交差している。【選択図】図1 |
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Bibliography: | Application Number: JP20220072511 |