SEMICONDUCTOR UNIT

• Main Author: IGARASHI SEIKI
• Format: Patent
• Language: English; Japanese
• Published: 02.11.2023
• Subjects: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS; BASIC ELECTRIC ELEMENTS; CONTROL OR REGULATION THEREOF; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERATION; SEMICONDUCTOR DEVICES

To equalize apportionment of a current at switching time among semiconductor modules connected in parallel to one another.SOLUTION: A laminated wiring 13 includes: a first conductor 13a which connects terminals 11a1-11d1 of capacitors 11a to 11d and each positive terminal 12a1-12f1 of a plurality of semiconductor modules 12a-12f; a second conductor 13b which connects terminals 11a2-11d2 of the capacitors 11a-11d and each negative terminal 12a2-12f2; and an insulator 13c. Slits 13a1-13a5, 13b1-13b5 are formed at least one of the first conductor 13a and the second conductor 13b (in both of them in the example of FIG. 1), and thereby among the semiconductor modules 12a-12f, a variation in a total of respective inductance values between the respective terminals 11a1-11d1 and one positive terminal 12a1-12f1 closest to the respective terminals and respective inductance values between the respective negative terminals 12a2-12f2 and one terminal 11a2-11d2 closest to the respective negative terminals is smaller than or equal to 10 nH.SELECTED DRAWING: Figure 1 【課題】並列に接続された半導体モジュール間のスイッチング時の電流分担を均等化する。【解決手段】ラミネート配線１３は、キャパシタ１１ａ～１１ｄの端子１１ａ１～１１ｄ１と半導体モジュール１２ａ～１２ｆの各正端子１２ａ１～１２ｆ１とを接続する第１導電体１３ａと、キャパシタ１１ａ～１１ｄの端子１１ａ２～１１ｄ２と各負端子１２ａ２～１２ｆ２とを接続する第２導電体１３ｂと、絶縁体１３ｃとを有する。ここで、第１導電体１３ａ及び第２導電体１３ｂの少なくとも一方（図１の例では両方）にスリット１３ａ１～１３ａ５，１３ｂ１～１３ｂ５を設けることで、端子１１ａ１～１１ｄ１から最も近い正端子１２ａ１～１２ｆ１までのインダクタンス値と、負端子１２ａ２～１２ｆ２から最も近い端子１１ａ２～１１ｄ２までのインダクタンス値との合計値のばらつきが半導体モジュール１２ａ～１２ｆの間で１０ｎＨ以下となるようにしている。【選択図】図１