SEMICONDUCTOR STORAGE DEVICE

• Main Authors: MAEDA TAKASHI, IKEGAMI KAZUTAKA, DOMAE SUMIKO, FUNATSUKI RIEKO
• Format: Patent
• Language: English; Japanese
• Published: 29.09.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

To provide a semiconductor storage device for suppressing erroneous reading of memory cells.SOLUTION: A semiconductor storage device includes: a first semiconductor pillar having i pieces of first memory cells connected in series and i pieces of second memory cells connected in series; i pieces of first word lines connected to i pieces of the first memory cells; i pieces of second word lines laminated in a second direction and connected to i pieces of the second memory cells; a driver capable of supplying voltage to each of i pieces of the first word lines and i pieces of the second word lines; and a logic control circuit for controlling writing operations and reading operations of i pieces of the first memory cells and i pieces of the second memory cells. A verify operation includes a channel clean operation for supplying a reference voltage to i pieces of the first memory cells and i pieces of the second memory cells and a sense operation for determining whether or not two or more threshold voltages are reached. The channel clean operation is executed twice and the sense operation is executed once after the second channel clean operation.SELECTED DRAWING: Figure 26 【課題】メモリセルの誤読み出しを抑制すること。【解決手段】半導体記憶装置は、直列に接続されたｉ個の第１メモリセルと、直列に接続されたｉ個の第２メモリセルと、を有する第１半導体ピラーと、ｉ個の第１メモリセルに接続されたｉ本の第１ワード線と、第２方向に積層されｉ個の第２メモリセルに接続されたｉ本の第２ワード線と、ｉ本の第１ワード線とｉ本の第２ワード線とのそれぞれに電圧を供給可能なドライバと、ｉ個の第１メモリセルとｉ個の第２メモリセルの書き込み動作及び読み出し動作を制御するロジック制御回路と、を有し、ベリファイ動作は、ｉ個の第１メモリセル及びｉ個の第２メモリセルに基準電圧が供給されるチャネルクリーン動作と、２通り以上の閾値電圧に到達しているか否かを判定するためのセンス動作とを含み、チャネルクリーン動作が２回実行され、２回目のチャネルクリーン動作の後に１回のセンス動作が実行される。【選択図】図２６