METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT AND LIGHT EMITTING ELEMENT
To provide a method of manufacturing a light emitting element, in which processes are simplified, and a light emitting element.SOLUTION: A method of manufacturing a light emitting element includes: a step of preparing a semiconductor laminate having a first region that includes an n-side semiconduct...
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Main Author | |
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Format | Patent |
Language | English Japanese |
Published |
04.08.2023
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a method of manufacturing a light emitting element, in which processes are simplified, and a light emitting element.SOLUTION: A method of manufacturing a light emitting element includes: a step of preparing a semiconductor laminate having a first region that includes an n-side semiconductor layer, an active layer, and a p-side semiconductor layer in a lamination direction of the semiconductor laminate, and a second region that does not include the active layer and the p-side semiconductor layer and includes the n-side semiconductor layer in the lamination direction, the second region being located around the first region in a plan view; a step of forming a mask having a plurality of first portions on a surface of the n-side semiconductor layer in the first region; and a step of removing the semiconductor laminate exposed from the mask, in which separation grooves that separate the semiconductor laminate into a plurality of semiconductor portions by removing the n-side semiconductor layer in the second region are formed and the first portions are removed while a plurality of protrusions are formed in the n-side semiconductor layer in the first region by removing the surroundings of the first portions in the n-side semiconductor layer in the first region.SELECTED DRAWING: Figure 9
【課題】工程が簡略化された発光素子の製造方法及び発光素子を提供すること。【解決手段】発光素子の製造方法は、半導体積層体の積層方向においてn側半導体層、活性層、及びp側半導体層を含む第1領域と、平面視において第1領域の周囲に位置し、積層方向において活性層及びp側半導体層を含まずn側半導体層を含む第2領域とを有する半導体積層体を準備する工程と、第1領域のn側半導体層の表面に複数の第1部分を有するマスクを形成する工程と、マスクから露出した半導体積層体を除去する工程であって、第2領域のn側半導体層を除去することで半導体積層体を複数の半導体部に分離する分離溝を形成するとともに、第1領域のn側半導体層のうち第1部分の周囲を除去することで第1領域のn側半導体層に複数の凸部を形成しつつ、第1部分を除去する工程と、を備える。【選択図】図9 |
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Bibliography: | Application Number: JP20220009471 |