SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE

• Main Authors: SUGAWARA KATSUTOSHI, ISHIBASHI KAZUYA
• Format: Patent
• Language: English; Japanese
• Published: 31.07.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor device capable of preventing a decrease in breakdown voltage and suppressing expansion of belt-like stacking faults.SOLUTION: A semiconductor device 101 comprises a cell region 50 electrically conducting a main current, a segmentation region 51 for segmenting the cell region 50 in a belt-like stacking fault expansion direction, and a termination region 56 provided around the cell region 50. The segmentation region 51 comprises a semiconductor layer 15 including a drift region 2 of a first conductivity type and a second well region 3B of a second conductivity type provided on the drift region 2, a second interlayer insulation film 8B provided on the semiconductor layer 15, and a source electrode 10 provided on the second interlayer insulation film 8B. The second interlayer insulation film 8B is arranged side by side in the belt-like stacking fault expansion direction, and includes two second contact holes 9B electrically connecting the source electrode 10 to the second well region 3B. The second well region 3B is formed in one region continuous in the belt-like stacking fault expansion direction in a region sandwiched between two second contact holes 9B in a top view.SELECTED DRAWING: Figure 3 【課題】耐圧低下を防止しつつ、帯状積層欠陥の拡張を抑制できる半導体装置を提供する。【解決手段】半導体装置１０１は、主電流を通電するセル領域５０と、帯状積層欠陥の拡張方向にセル領域５０を分断する分断領域５１と、セル領域５０の周囲に設けられた終端領域５６とを有し、分断領域５１では、第１導電型のドリフト領域２と、ドリフト領域２の上に設けられた第２導電型の第２ウェル領域３Ｂとを含む半導体層１５、半導体層１５の上に設けられた第２層間絶縁膜８Ｂ、及び、第２層間絶縁膜８Ｂの上に設けられたソース電極１０を備える。第２層間絶縁膜８Ｂは、帯状積層欠陥の拡張方向に並んで配置され、ソース電極１０を第２ウェル領域３Ｂと電気的に接続する２つの第２コンタクトホール９Ｂを有する。第２ウェル領域３Ｂは、上面視して２つの第２コンタクトホール９Ｂに挟まれた領域において帯状積層欠陥の拡張方向に連続する１つの領域で形成される。【選択図】 図３