SEMICONDUCTOR DEVICE

• Main Author: YAMAJI MASAHARU
• Format: Patent
• Language: English; Japanese
• Published: 26.06.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

To provide a semiconductor device capable of reducing the chip size when forming a plurality of structures having mutually independent high voltage behavior on the same chip.SOLUTION: A semiconductor device includes a semiconductor substrate 1, a first conductivity type first region 2 selectively provided on an upper portion of the semiconductor substrate 1, a second conductivity type second region 4 provided in contact with the first region 2 on the upper part of the semiconductor substrate 1, a second conductivity type third region 5 provided on the semiconductor substrate 1 and spaced apart from the second region 4, a second conductivity type fourth region 3 provided between the second region 4 and the third region 5 on the upper part of the semiconductor substrate 1. a first isolation region 31 provided between the second region 4 and the fourth region 3, and a second separation region 32 provided between the third region 5 and the fourth region 3.SELECTED DRAWING: Figure 3 【課題】互いに独立した高電圧挙動となる複数の構造を同一チップに形成する場合に、チップサイズを縮小することができる半導体装置を提供する。【解決手段】半導体基体１と、半導体基体１の上部に選択的に設けられた第１導電型の第１領域２と、半導体基体１の上部に第１領域２に接して設けられた第２導電型の第２領域４と、半導体基体１の上部に第２領域４から離間して設けられた第２導電型の第３領域５と、半導体基体１の上部の第２領域４と第３領域５の間に設けられた第２導電型の第４領域３と、第２領域４と第４領域３の間に設けられた第１分離領域３１と、第３領域５と第４領域３の間に設けられた第２分離領域３２とを備える。【選択図】図３