SILICON WAFER AND EPITAXIAL SILICON WAFER
To reduce a dislocation loop defect density which causes a lamination defect in a silicon wafer.SOLUTION: There is provided a silicon wafer having a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×1016 atoms/cm3 or...
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Format | Patent |
Language | English Japanese |
Published |
18.05.2023
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Abstract | To reduce a dislocation loop defect density which causes a lamination defect in a silicon wafer.SOLUTION: There is provided a silicon wafer having a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×1016 atoms/cm3 or more.SELECTED DRAWING: Figure 5
【課題】シリコンウェーハにおいて、積層欠陥の原因となる転位ループ欠陥密度を少なくする。【解決手段】直径が200mmであり、ドーパントがリンであり、抵抗率が0.5mΩ・cm以上1.2mΩ・cm以下、かつ、炭素濃度が3×1016atoms/cm3以上であるシリコンウェーハを提供する。【選択図】図5 |
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AbstractList | To reduce a dislocation loop defect density which causes a lamination defect in a silicon wafer.SOLUTION: There is provided a silicon wafer having a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×1016 atoms/cm3 or more.SELECTED DRAWING: Figure 5
【課題】シリコンウェーハにおいて、積層欠陥の原因となる転位ループ欠陥密度を少なくする。【解決手段】直径が200mmであり、ドーパントがリンであり、抵抗率が0.5mΩ・cm以上1.2mΩ・cm以下、かつ、炭素濃度が3×1016atoms/cm3以上であるシリコンウェーハを提供する。【選択図】図5 |
Author | NARUSHIMA YASUTO KOGA KOTARO ONO TOSHIAKI HORAI MASATAKA NONAKA NAOYA |
Author_xml | – fullname: NONAKA NAOYA – fullname: NARUSHIMA YASUTO – fullname: ONO TOSHIAKI – fullname: HORAI MASATAKA – fullname: KOGA KOTARO |
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DocumentTitleAlternate | シリコンウェーハおよびエピタキシャルシリコンウェーハ |
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Snippet | To reduce a dislocation loop defect density which causes a lamination defect in a silicon wafer.SOLUTION: There is provided a silicon wafer having a diameter... |
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SubjectTerms | AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUSPOLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE APPARATUS THEREFOR BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL CRYSTAL GROWTH DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE REFINING BY ZONE-MELTING OF MATERIAL SEMICONDUCTOR DEVICES SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE SINGLE-CRYSTAL-GROWTH SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL ORUNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL |
Title | SILICON WAFER AND EPITAXIAL SILICON WAFER |
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