SILICON WAFER AND EPITAXIAL SILICON WAFER

To reduce a dislocation loop defect density which causes a lamination defect in a silicon wafer.SOLUTION: There is provided a silicon wafer having a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×1016 atoms/cm3 or...

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Bibliographic Details
Main Authors NONAKA NAOYA, NARUSHIMA YASUTO, ONO TOSHIAKI, HORAI MASATAKA, KOGA KOTARO
Format Patent
LanguageEnglish
Japanese
Published 18.05.2023
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Summary:To reduce a dislocation loop defect density which causes a lamination defect in a silicon wafer.SOLUTION: There is provided a silicon wafer having a diameter of 200 mm, a dopant of phosphorus, a resistivity of 0.5 mΩ cm or more and 1.2 mΩ cm or less, and a carbon concentration of 3×1016 atoms/cm3 or more.SELECTED DRAWING: Figure 5 【課題】シリコンウェーハにおいて、積層欠陥の原因となる転位ループ欠陥密度を少なくする。【解決手段】直径が200mmであり、ドーパントがリンであり、抵抗率が0.5mΩ・cm以上1.2mΩ・cm以下、かつ、炭素濃度が3×1016atoms/cm3以上であるシリコンウェーハを提供する。【選択図】図5
Bibliography:Application Number: JP20220093899