SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

To suppress increase in a manufacturing process.SOLUTION: A semiconductor package includes a semiconductor chip 20 formed with a semiconductor element, an insulating/heat dissipating member 10 mounted with a semiconductor chip 10, and a sealing member 30 for sealing the semiconductor chip 20. The se...

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Bibliographic Details
Main Author IMAIZUMI NORIHISA
Format Patent
LanguageEnglish
Japanese
Published 15.03.2023
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Summary:To suppress increase in a manufacturing process.SOLUTION: A semiconductor package includes a semiconductor chip 20 formed with a semiconductor element, an insulating/heat dissipating member 10 mounted with a semiconductor chip 10, and a sealing member 30 for sealing the semiconductor chip 20. The sealing member 30 has a resin part 31 composed of a liquid crystal polymer, and a wiring part 32 electrically connected to the semiconductor chip 20, the wiring part 32 has a plurality of wiring layers 322 extending in a surface direction of the semiconductor chip 20, and a connection via 321 which extends in a lamination direction of the semiconductor chip 20 and the insulating/heat dissipating member 10 and connects the adjacent wiring layer 322 in the lamination direction, and the wiring layer 322 and the connection via 321 are composed of a sintered body.SELECTED DRAWING: Figure 1 【課題】製造工程が増加することを抑制する。【解決手段】半導体素子が形成された半導体チップ20と、半導体チップ10を搭載する絶縁放熱部材10と、半導体チップ20を封止する封止部材30とを備える。封止部材30は、液晶ポリマで構成された樹脂部31と、半導体チップ20と電気的に接続される配線部32とを有し、配線部32は、半導体チップ20の面方向に沿って延びる複数の配線層322と、半導体チップ20と絶縁放熱部材10との積層方向に沿って延び、積層方向に沿って隣合う配線層322を接続する接続ビア321とを有し、配線層322および接続ビア321は、焼結体で構成されるようにする。【選択図】図1
Bibliography:Application Number: JP20210143931