ELECTRONIC INTERLOCKING DEVICE AND COMPUTER PROGRAM

To making it possible to integrate and process interlocking functions of many stations.SOLUTION: An electronic interlocking device 1 is connected to a plurality of on-site apparatuses 2 including a signal 21, a point machine 22, and a train position detection device 23. The electronic interlocking d...

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Bibliographic Details
Main Authors HASEGAWA TOMOKI, MORI TAKASHI
Format Patent
LanguageEnglish
Japanese
Published 16.02.2023
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Summary:To making it possible to integrate and process interlocking functions of many stations.SOLUTION: An electronic interlocking device 1 is connected to a plurality of on-site apparatuses 2 including a signal 21, a point machine 22, and a train position detection device 23. The electronic interlocking device 1 includes an interlocking processing unit 3 performing arithmetic processing. The interlocking processing unit 3 has a sequential logic unit 32. The sequential logic unit 32 executes course locking processing. The sequential logic unit 32 has a plurality of comparison functions FC, a plurality of establishment conditions C, an internal state variable q, and an internal state function Fi. When an input variable x is input in the sequential logic unit 32, it is determined whether or not the input variable x and the internal state variable q coincide with the establishment conditions C by each comparison function FC. If they coincide with each other, the processing of outputting an output variable z corresponding to the establishment condition C is periodically repeated. The internal state function Fi is input with the input variable x and the output variable z and an internal state variable q of the next period is output. The sequential logic unit 32 calculates the plurality of comparison functions FC in parallel in the processing in each period.SELECTED DRAWING: Figure 1 【課題】多くの駅の連動機能を集約して処理できるようにする。【解決手段】電子連動装置1は、信号機21及び転てつ機22並びに列車位置検知装置23を含む複数の現場機器2と接続される。電子連動装置1は、演算処理を行う連動処理部3を備える。連動処理部3は、順序論理部32を有する。順序論理部32は、進路鎖錠の処理を実行する。順序論理部32は、複数の比較関数FCと、複数の成立条件Cと、内部状態変数qと、内部状態関数Fiとを有する。順序論理部32は、入力変数xが入力されて、入力変数x及び内部状態変数qが成立条件Cに合致するか否かを各比較関数FCで判別して、合致するとき、その成立条件Cに対応する出力変数zを出力する処理を周期的に繰り返す。内部状態関数Fiは、入力変数x及び出力変数zが入力されて、次の周期の内部状態変数qを出力する。順序論理部32は、各周期内の処理において複数の比較関数FCを並列に演算する。【選択図】図1
Bibliography:Application Number: JP20210128826